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Altera EPM7128B

提供CPLD EPM7128B解密服务,仅限学习、研究等合法用途,解密热线:010-62245566 13810019655
有EPM7128B单片机解密等CPLD解密需求者请直接与我们联系咨询详情。
EPM7128B 可解密的型号如下:
EPM7128BTC48-10
EPM7128BTC48-7
EPM7128BTC48-4
EPM7128BUC49-10
EPM7128BUC49-7
EPM7128BUC49-4
EPM7128BTC100-10
EPM7128BTC100-7
EPM7128BTC100-4
EPM7128BTI100-7
EPM7128BFC100-10
EPM7128BFC100-7
EPM7128BFC100-4
EPM7128BFI100-7
EPM7128BTC144-10
EPM7128BTC144-7
EPM7128BTC144-4
EPM7128BUC169-10
EPM7128BUC169-7
EPM7128BUC169-4
EPM7128BFC256-10
EPM7128BFC256-7
EPM7128BFC256-4
EPM7128BFI256-7
EPM7128B 特性如下,详细资料见EPM7128B.pdf
EPM7128B解密
■ High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX
(MAX?) architecture (see Table 1)
– Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V MAX 7000A device families
– High-density PLDs ranging from 600 to 10,000 usable gates
– 3.5-ns pin-to-pin logic delays with counter frequencies in excess of 303.0 MHz
■ Advanced 2.5-V in-system programmability (ISP)
– Programs through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in-system programming
– ISP circuitry compliant with IEEE Std. 1532

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