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Altera EPM7160E

提供CPLD EPM7160E解密服务,仅限学习、研究等合法用途,解密热线:010-62245566 13810019655
我们多年来一直专注与各类专用IC解密、CPLD解密等技术研究领域,经过长期的项目攻关,我们已经成功取得系列技术突破,目前可提供多个系列IC芯片及单片机解密技术服务,致力于为广大的电子企业及电子工程师提供全方位技术支持。
EPM7160E 可解密的型号如下:
EPM7160ELC84-20
EPM7160ELC84-15
EPM7160ELC84-12
EPM7160ELC84-10
EPM7160ELI84-20
EPM7160EQC100-20
EPM7160EQC100-15
EPM7160EQC100-12
EPM7160EQC100-10
EPM7160EQC100-10P
EPM7160EQI100-15
EPM7160EQC160-20
EPM7160EQC160-15
EPM7160EQC160-12
EPM7160EQC160-10
EPM7160EQC160-10P
EPM7160EQI160-15
Altera EPM7160E 特性如下,详细资料见EPM7160E.pdf
■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX? architecture
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells
■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)
■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
■ PCI-compliant devices available

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