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Altera EPM7192E

提供CPLD EPM7192E解密服务,仅限学习、研究等合法用途,解密热线:010-62245566 13810019655
EPM7192E 芯片解密需求者请与北京都信联系,我们长期以CPLD解密、单片机解密、疑难芯片解密等为主流研究项目,在各个研究领域均以取得重大突破,可提供安全可靠,价格合理的高质量解密服务。
EPM7192E 可解密的型号如下:
EPM7192EQC160-20
EPM7192EQC160-15
EPM7192EQC160-12
EPM7192EQC160-12P
EPM7192EQI160-20
EPM7192EGC160-20
EPM7192EGC160-15
EPM7192EGC160-12
EPM7192EGI160-20
EPM7192E 特性如下,详细资料见EPM7192E.pdf
■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX? architecture
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells
■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates
■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
■ PCI-compliant devices available

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